The present invention relates to semiconductor memory devices, and more particularly, to phase-change semiconductor memory devices and operating methods therefor.
Semiconductor memory devices are widely used devices for storing data and may be largely divided into random access memory (RAM) and read-only memory (ROM). ROM is nonvolatile memory that can retain stored data even when not powered. Examples of ROM are programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory. RAM is volatile memory where stored data is lost when power supply is interrupted. Examples of RAM are dynamic RAM (DRAM) and static RAM (SRAM). Moreover, semiconductor memory devices have been introduced that replace a capacitor with a non-volatile material in a DRAM-like architecture. Examples of these semiconductor memory devices are ferroelectric RAM devices using ferroelectric capacitors, magnetic RAM (MRAM) devices using tunneling magneto-resistive (TMR) films, and phase-change memory devices using chalcogenide alloys. The phase-change memory devices are non-volatile memory devices using phase change, i.e., resistance change over temperature.
FIG. 1 illustrates a memory cell 1 in a phase-change memory device. Referring to FIG. 1, the memory cell 1 includes a memory element 2 and a selection element 3. The memory element 2 is connected between a bit line BI, and the selection element 3. The selection element 3 is connected with the memory element 2, a ground, and a word line WL. Alternatively, the selection element 3 may be connected between the bit line BL and the memory element 2.
The memory element 2 includes a phase-change material. The phase-change material is a variable resistor whose resistance varies with temperature, such as Ge—Sb—Te. The phase-change material has one of two stable states, i.e., a crystal state and an amorphous state according to temperature. The phase-change material changes to the crystal state or the amorphous state according to current supplied through the bit line BL. The phase-change memory device can store data of “1” or “0” in the memory element 2 using this characteristic of the phase-change material.
FIG. 2 is a block diagram of a core structure in a phase-change memory device 10 according to an embodiment of the prior art. Referring to FIG. 2, the phase-change memory device 10 includes a memory cell array. The memory cell array may include a plurality of memory banks 10_1 through 10_16 each of which includes a plurality of phase-change memory cells arranged in a matrix form.
Sense amplifiers/write drivers (SA/WD) 30_1 through 30_16 are respectively disposed in the memory banks 10_1 through 10_16 to perform a read operation and a write operation. Global bit line selection circuits (GYPASS) 20_1 through 20_16 are respectively disposed in the memory banks 10_1 through 10_16. Each of the global bit line selection circuits 20_1 through 20_16 selectively connects a plurality of global bit lines GBL to a corresponding one of the sense amplifiers/write drivers 30_1 through 30_16. The phase-change memory device 10 also includes a local bit line selection circuit (not shown) to selectively connect a plurality of local bit lines (not shown) to one of the global bit lines GBL.
It will be understood that the block diagram of FIG. 2 and the remaining block diagrams herein provide an electrical schematic diagram illustrating the electrical interconnection of the various elements and, in some embodiments, may also illustrate the relative locations of these elements in a semiconductor memory device.
When the phase-change memory device 10 is tested, it may be desirable to write test data to a plurality of memory cells at the same time in order to reduce a testing time. Accordingly, it may be desirable to select two or more memory banks at one time.
When a phase-change memory device having the structure illustrated in FIG. 2, in which the sense amplifiers/write drivers 30_1 through 30_16 are respectively disposed in the memory banks 10_1 through 10_16, is tested, a plurality of memory banks can be selected at one time to write data thereto since the sense amplifiers/write drivers 30_1 through 30_16 are separately provided for the respective memory banks 10_1 through 10_16. Accordingly, with respect to the phase-change memory device 10 illustrated in FIG. 2, two or more memory banks (e.g., 10_1 and 10_2) among the memory banks 10_1 through 10_16 can be simultaneously selected for multi-writing, so that a testing time can be reduced.
In contrast, when a phase-change memory device having a structure, in which the plurality of the memory banks share sense amplifiers and write drivers, is tested, it may be difficult to select a plurality of memory banks at one time and write data thereto with a single write driver. If a plurality of memory banks are selected, data is written to memory cells in the plurality of memory banks through a single write driver. In a normal write operation, data is written to a single memory cell through a single write driver, and therefore, the write driver can make current having enough (e.g., desired) magnitude to write data flow to the memory cell. In a case of test in which a plurality of memory banks are selected and data is written to the memory banks with a single write driver, a mode has different conditions than a normal write mode.